Feed-forward control of tci doping for improving mass-production-wise, statistical distribution of critical performance parameters in semiconductor devices

ABSTRACT

When Tilted Channel Implant (TCI) is performed on transistor precursor structures having an etch-defined gate length (L 2M ) and a trim-defined sidewall thickness (S wM ), mass production deviations may cause errors between targeted values for these critical dimensions (CD&#39;s) and the correspondingly measured CD&#39;s. These deviations may respectively cause shifts in the lateral placement of TCI dopants or in the depth of implant of the TCI dopants, thereby tending to cause variation in final device characteristics. Countering adjustments to TCI dosage and TCI energy are automatically made in accordance with the invention. These countering adjustments in the TCI process enable expansion of tolerance ranges in pre-TCI production steps, thereby increase manufacturing yield.

CROSS-REFERENCE TO CO-OWNED PATENT APPLICATIONS

[0001] This application is a concurrent continuation-in-part of U.S.patent application Ser. No. _______, which application is owned by theowner of the present application and which application is concurrentlyfiled herewith on behalf of the same inventors, Zoran Krivokapic andWilliam D. Heavlin, and which parent application is initially entitledFEED-FORWARD CONTROL OF TCI DOPING FOR IMPROVING MASS-PRODUCTION-WISE,STATISTICAL DISTRIBUTION OF CRITICAL PERFORMANCE PARAMETERS INSEMICONDUCTOR DEVICES, and whose disclosure is incorporated herein byreference.

BACKGROUND

[0002] 1. Field of Invention

[0003] The invention is generally directed to the mass production ofsemiconductor devices. The invention is more specifically directed tothe problem of tightening statistical variation of critical performanceparameters during mass production of semiconductor devices, where thefabrication process includes TCI (Tilted Channel Implant) doping.

[0004] 2a. Cross Reference to Issued Patents

[0005] The disclosures of the following U.S. patents are incorporatedherein by reference:

[0006] (A) Pat. No. 5,926,690 issued Jul., 20, 1999 to Toprac, et al,and entitled, Run-to-run Control Process for Controlling CriticalDimensions; and

[0007] (B) Pat. No. 5,863,824 issued Jan. 26, 1999 to Gardner, et al,and entitled, Method of Forming Semiconductor Devices Using GateElectrode Length and Spacer Width for Controlling Drive CurrentStrength.

[0008] 2b. Description of Related Art

[0009] A mass-production tolerance problem emerges as thehistorically-consistent, and industry-pervasive, shrinkage for theeffective length (L_(eff)) of transistor channels continues on tosmaller and smaller dimensions. Statistical variations tend to crop upover time in the mass-production processes that ultimately defineeffective channel length (L_(eff)) Of importance, such statisticalvariations show up in what may termed as critical dimensions (CD's) ofin-process structures.

[0010] More specifically, it is predicted that shrinkage of dimensionswill continue as it had in the past, with the implementation of eversmaller dimensions of channel length, such as moving from devices withchannel lengths of about 0.25 μ (0.25 micron) or less, down to deviceswith channel lengths of about 0.18 μ or less, and then continuing downto devices with channel lengths of about 0.09 μ or less, and perhapscontinuing to even substantially smaller dimensions. As these dimensionsshrink, the so-called ‘critical dimensions’ (CD's) oftransistor-precursor structures (which structures appear duringmass-production) become more and more difficult to control withprecision. At the same time, the mass-production replication of suchCD's becomes more significant to final device performance as channellength dimensions shrink. New methods are needed for providing tighterprocess control of critical performance parameters so that desiredstatistical mean and 3 sigma (3 σ) values can be obtained formass-produced devices.

[0011] One factor that can play a substantial role in determining theultimate L_(eff) of each individual one of mass-produced transistors isthe precision with which the actual length of the patterned gatematerial (e.g., polysilicon) can be controlled. This patterned gatematerial is that which remains in the transistor-precursor structureafter completion of mass-production photomasking, mass-production resisttrimming, and mass-production gate-material etch.

[0012] Another factor that can play a role in determining the ultimateL_(eff), in cases where sidewall spacers are formed and trimmed aboutthe post-etch gate, is the precision to which the deposition andtrimming of such sidewalls is carried out.

[0013] The interplay between such factors will become more apparent whenthe drawings are described in detail below. For now, it is sufficient tounderstand how, in a conventional fabrication process, an ideal ortarget value (L_(GateT)) is established for the final length of the gatematerial that remains after gate-layer etching. Due to statisticalprocess variations, and even though the measured, actual gate length(the gate FICD) will tend to have an average or mean value that is closeto the ideal or target value (L_(GateT)), individually-sampled dice orwafers or lots will tend to exhibit gate FICD's (Final Inspectionmeasurements of Critical Dimension) that deviate by finite amounts fromthe target value. In other words, there will typically be amanufacturing tolerance error that may be expressed as:

e _(Gate) =L _(GateT)−^(FICD)  {Eq. 1}.

[0014] The group of fabrication technicians and/or other personnel whoare responsible for keeping the post-etch gate length (as measured byFICD) close to the established ideal or target value (L_(GateT)), willtypically define an allowed tolerance-range, e₁≦e_(Gate)≦e₂ (where e₁ istypically less than zero while e₂ is greater than zero). Nonconforming,post-etch wafers will usually be thrown away.

[0015] If, at a given time during production, a statisticallysignificant number of FICD measurements begin to fall outside thepredefined, allowed tolerance-range, e₁≦e_(Gate)≦e₂, then productionmight need to be temporarily halted to find out why there is an such anunusual increase in the number of nonconforming, post-etch wafers.Specialty personnel (e.g., gate-etch control engineers) may have to becalled in to determine what, if any, fine tunings should be made to thegate-etch process to bring its statistical results (mean and 3 σdeviation) back to acceptable numbers.

[0016] This is risky business. Sometimes an observed set of extremedeviations is just a random coincidence and the correct response (as canbe shown only by hindsight) is to leave the gate-etch process unchanged.If a fine-tuning is nonetheless applied, that tuning may itself, overtime, cause an even larger number of wafers to fall outside the allowedtolerance-range, e₁≦e_(Gate)≦e₂.

[0017] Further downstream along the mass-production line, there may be asecond group of fabrication personnel who are responsible for applying(depositing) and trimming down, gate sidewalls. This second group willface a similar dilemma. They will establish statistical mean and alloweddeviation ranges for sidewall film thickness and trim-down distance. Theallowed range may be expressed as, e₃≦esidewall≦e₄, where e_(Sidewall)is the error between measured and target thickness dimensions for thegate sidewalls, and e₃ is typically less than zero while e₄ is greaterthan zero. Nonconforming, post-trim wafers may have to be thrown away orstripped and re-worked.

[0018] If a statistically significant number of sidewall-thicknessmeasurements begin to come back as falling outside the allowedtolerance-range, e₃≦e_(Sidewall)≦e₄, then production might need to betemporarily halted. Specialty personnel (e.g., sidewall-deposition andtrim control engineers) may have to be called in to determine what, ifany, fine tunings should be made to the sidewall-deposition and/orsidewall-trim processes to bring their statistical results (mean and 3 σdeviation) back to acceptable numbers. Like the case involving finetuning of the gate-etch process, fine tuning of the sidewall-depositionand/or sidewall-trim processes is risky business. Sometimes an observedset of extreme deviations is just a random coincidence and the correctresponse is to leave the sidewall-related processes unchanged. If afine-tuning is nonetheless applied, that tuning may over time, push aneven larger number of samples outside the allowed tolerance-range.

[0019] It is seen from the above that CD measurement practices andstatistical analysis and response practices can produce dilemmas. On theone hand, semiconductor manufacturers want to obtain good yield of finalproduct in as little time as possible. On the same hand, they want toavoid the costs of human intervention. On the other hand, they want toavoid the possible errors of human judgment that might come to play withconstant, manually-determined fine tunings to each gate etch or sidewalldeposition or sidewall trim process. To achieve the end result ofavoiding judgment errors, it has been generally accepted that the gateFICD's (measured critical dimensions) must be maintained within verytight tolerances, even if that goal leads to a throwing away of largenumbers of post-etch wafers. But that means that yield suffers. It is asituation that leaves practitioners in a can't-win dilemma. They cansuffer yield loss by taking either choice, namely, (a) throwing awaylarge numbers of wafers and not re-tuning the production line, or (b)re-tuning the production line and, in cases where the re-tune containshuman error, losing productivity because of the human judgment error.

[0020] Practices in accordance with the present invention offer win/winalternatives, in other words, those that can help to automaticallyreclaim what were previously considered out-of-specification dice orwafers without placing production personnel on the horns of a lose/losedilemma. The present invention can improve final yield while at the sametime avoiding the possible errors of human judgment that might come toplay with constant, manually-determined fine tunings to processes thataffect critical dimensions.

SUMMARY OF INVENTION

[0021] Signals representing manufacturing tolerance errors in one orboth of gate length (eGate) and sidewall thickness (eSidewall) are fedforward in accordance with the invention to a variable TCI process. Theenergy and/or dosage values used in the Tilted Channel Implant (TCI)process are automatically adjusted in response. The variability of theenergy and/or dosage values provides additional controls which can beautomatically fine-tuned in accordance with the invention to countermanufacturing tolerance errors that occur in mass-production defining ofgate length and sidewall thickness. Such error feed forward methods maybe used in accordance with the invention for improving mass-productionstatistical distribution of critical parameters in semiconductordevices.

[0022] An automated production system in accordance with the inventioncomprises: (a) a variable TCI process having at least one of variableenergy and variable dosage capabilities; and (b) feed-forward means forfeeding forward to the variable TCI process, error signals representingmanufacturing tolerance errors in one or both of gate length (e_(Gate))and sidewall thickness (e_(Sidewall)), wherein at least one of said,variable energy and variable dosage capabilities of the TCI process isadjusted in response to the fed-forward error signals (e_(Gate),e_(Sidewall)) to counter the effects of the error.

[0023] A mass-production method in accordance with the inventioncomprises the steps of: (a) defining a target, statistical mean value(L_(2T)) for gate length; (b) defining a target, statistical mean value(S_(wT)) for thickness of gate sidewalls; (c) measuring error(L_(2T)−L_(2M)) in gate length of a production sample; (d) measuringerror (S_(wM)−S_(wT)) in sidewall thickness of the production sample;(e) calculating an adjusted Tilted Channel Implant energy in response tothe measured error in sidewall thickness; (f) calculating an adjustedTilted Channel Implant dosage in response to the measured error in gatelength; and (g) performing a Tilted Channel Implant operation on saidproduction sample while using at least one of the adjusted energy andadjusted dosage during said TCI operation.

[0024] A machine-implemented and automated mass-production method inaccordance with the invention uses a pre-defined target, statisticalmean value (L_(2T)) for gate length and a pre-defined target,statistical mean value (S_(wT)) for thickness of gate sidewalls, andcomprises the steps of: (a) collecting first data representing error(L_(2T)−L_(2M)) in gate length of respective production samples; (b)collecting second data representing error (S_(wM)−S_(wT)) in sidewallthickness of the production samples; (c) for each non-zero error insidewall thickness, responsively calculating an adjustment in TiltedChannel Implant energy to be employed for the corresponding productionsample; (d) for each non-zero error in gate length, responsivelycalculating an adjustment in Tilted Channel Implant dosage to beemployed for the corresponding production sample; and (e) performing aTilted Channel Implant operation on each of said production sampleswhile using at least one of the corresponding energy adjustment andcorresponding dosage adjustment during said performance of the TCIoperation on each respective production sample that is indicated to havenon-zero error in gate length or sidewall thickness.

[0025] A method in accordance with the invention for optimizingautomated, feed-forward compensation for manufacturing tolerance errorsin one or both of gate length (e_(Gate)) and sidewall thickness(e_(Sidewall)), comprises the steps of: (a) defining a target,statistical mean value (L_(2T)) for gate length; (b) defining a target,statistical mean value (S_(wT)) for thickness of gate sidewalls; (c)determining a target, statistical mean value (V_(TT) or Q_(TT)) for acritical electrical characteristic of transistors manufactured to havesaid target gate length and said target sidewall thickness; (d)identifying first stray production samples that have a predefined firstamount of error (L_(2T)−L_(2M)) in gate length; (e) experimentallydetermining an amount of adjustment in Tilted Channel Implant dosagethat may be employed for the corresponding first stray productionsamples so as to bring the critical electrical characteristic oftransistors manufactured from said first stray production samples intoconformance with said target value (V_(TT) or Q_(TT)) for the criticalelectrical characteristic; (f) defining a dosage adjustmentinterpolation function for use when second stray production samples areidentified with gate length errors substantially close to saidpredefined first amount of error (L_(2T)−L_(2M)) in gate length; (g)identifying third stray production samples that have a predefined secondamount of error (S_(wM)-S_(wT)) in sidewall thickness; (h)experimentally determining an amount of adjustment in Tilted ChannelImplant energy that may be employed for the corresponding third strayproduction samples so as to bring the critical electrical characteristicof transistors manufactured from said third stray production samplesinto conformance with said target value (V_(TT) or Q_(TT)) for thecritical electrical characteristic; (i) defining an energy adjustmentinterpolation function for use when fourth stray production samples areidentified with sidewall thickness errors substantially close to saidpredefined second amount of error (S_(wM)-S_(wT)) in sidewall thickness;and (j) using at least one of said dosage and energy adjustmentinterpolation functions for establishing respective TCI dosage andenergy when subjecting further production samples to Tilted ChannelImplant.

[0026] A method for increasing the mass-production in-conformance rangefor one or both of a gate trimming process and a sidewall trimmingprocess in accordance with the invention comprises the steps of: (a)defining TCI dosage and energy adjustment functions for use in responseto respective detection of error (L_(2T)−L_(2M)) in gate length ofproduction samples and of error (S_(wM)−S_(wT)) in sidewall thickness ofproduction samples; and (b) in view of said TCI dosage and energyadjustment functions, expanding the allowed tolerance range that wouldhave been otherwise used if said TCI dosage and energy adjustmentfunctions had not been in place, the expanded tolerance range being atleast one for ADICD-defined error in photoresist (PR) trimming, or forFICD-defined error in gate etching, or for measured error in sidewalllayer deposition thickness, or for measured error in post-trim sidewallthickness. Other aspects of the invention will become apparent from thebelow detailed description.

BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The below detailed description makes reference to theaccompanying drawings, in which:

[0028]FIG. 1A is a cross sectional view of a first transistor-precursorstructure in which photoresist (PR) is isotropically trimmed tobelow-photolithography dimensions;

[0029]FIG. 1B is a cross sectional view of a second transistor-precursorstructure in which a gate substructure is formed by anisotropic etching;

[0030]FIG. 1C is a cross sectional view of a third transistor-precursorstructure in which a sidewall-forming film is deposited;

[0031]FIG. 1D is a cross sectional view of a fourth transistor-precursorstructure in which gate sidewalls are left behind by anisotropic etchingand trimmed;

[0032]FIG. 1E is a cross sectional view of a fifth transistor-precursorstructure in which a channel doping gradient is defined by TCI doping;

[0033]FIG. 1F is a further cross sectional view of the fifthtransistor-precursor structure for showing more clearly how criticaltransistor parameters, L_(eff) and L_(OV) can be defined by source anddrain implant steps and by preceding process steps;

[0034]FIG. 2 is a graph illustrating how fine-tuning of the PR-trimprocess can affect critical dimensions;

[0035]FIG. 3 is a combined schematic and further cross sectional viewshowing the operations of an automated feedforward system in accordancewith the invention;

[0036]FIG. 4A is a graph for explaining how TCI doping energy may beadjusted to counter error in sidewall thickness, which error can changeeffective channel length;

[0037]FIG. 4B is a graph for explaining how TCI doping dosage may beadjusted to counter error in gate length, which error can change theeffective threshold voltage; and

[0038]FIGS. 5A and 5B combine to provide a block diagram showing how thein-conformance range of one or both of a gate trimming process andsidewall deposition and/or trimming processes can be widened;

DETAILED DESCRIPTION

[0039]FIG. 1A is a cross-sectional view of a first in-process structure100 (transistor-precursor structure 100) that may occur duringmass-production of integrated circuits.

[0040] Precursor structure 100 may be arrived at as follows. Alightly-doped (e.g., P-) semiconductor substrate 110 such as one formedof monocrystalline silicon or another suitable material is provided. Athin layer of gate-insulating oxide (GoX) or of another suitablematerial is thermally grown or otherwise formed on the substrate 110. Agate-forming material such as polycrystalline silicon or anothersuitable material is deposited by CVD process or by other means todefine a gate-precursor layer 114 (e.g., poly-1) on top of the GoX Layer112. An anti-reflective coating (ARC) such as made of an oxynitride (ON)material 116 may be provided on the gate layer 114. Photoresist (PR) isdeposited on the resulting precursor structure. Photo-lithographicallyor like feature-defining methods are used to pattern and develop PRfeatures such as 119 to have initial dimensions such as the illustratedfirst length, L1.

[0041] Because of limitations in photolithographic or otherfeature-defining processes, there is typically a constraint on how smallthe first dimension L1 may be. For example, in one process the desiredor target value for L1 may be limited to being no smaller than about 200nanometers (0.200 μ). A first metrology step 121 may be carried out tomeasure the actual L1 dimension of plural production samples and toproduce a corresponding DICD₁ or ADICD₁ (After-Development Inspection ofCritical Dimension) measurement value.

[0042] Isotropic etching of selected ones or all of the patterned PRlayer features is typically employed to trim the anisotropically-etchedphotoresist 119 to sub-lithography dimensions. In FIG. 1A, theoriginally patterned photoresist is shown as dashed outline 119 with thecorresponding first length dimension, L1, while the post-trimphotoresist is shown as hatched block 118 with a corresponding secondlength dimension, L2 (where L2<L1). In one exemplary process the desiredor target value for L2 may be about 140 nanometers (0.140 μ).

[0043] A second metrology step 122 may be used to measure the L2dimension of plural production samples and to produce a correspondingDICD₂ or ADICD₂ measurement value. One or the other of metrology steps121 and 122 may be bypassed if desired, or both may be carried out.

[0044] Referring to FIG. 2, either or both of the pre-trim DICD₁measurement value and the post-trim DICD₂ measurement value may beobtained as follows. After the respective formation of the pre-trim,anisotropically-etched photoresist feature 119 or the post-trim,isotropically-etched photoresist feature 118, samples of the dice,wafers or other mass-produced articles in which precursor structure 100is repeatedly found are sent to a respective metrology station(schematically shown as 121 and 122 respectively) for measurement anddetermination of the average per-wafer and/or per wafer-lot values ofthe respective length dimension, L1 or L2, and of its statisticaldistribution at various points of the wafer (e.g., a 9-point star test)and across the respective production lot. Such measurement andcalculation steps provide the corresponding DICD or ADICD measurementvalues.

[0045] If the per-wafer, measured average value, L_(M) of thepre/post-trim dimension, L1/L2 and its distribution closely match arespective target value, L_(1T) or L_(2T), then the PR trim process isleft as is and further batches of wafers are trimmed with the samePR-trim settings.

[0046] For each wafer or other sample, there will typically be amanufacturing tolerance error that may be expressed as,e_(GatePR)=L_(PRT)−ADICD, where L_(PRT) represents the desired or targetvalue for the developed photoresist (either before or after PR trimmingprocess respectively depending on whether ADICD represents measurementof the L1 or the L2 dimension). The group of fabrication personnel whoare responsible for keeping the respective pre-trim or post-trim PRlength (ADICD) close to the established ideal or target value (L_(1T) orL_(2T)), will typically define an allowed tolerance-range,e₁′≦e_(GatePR)≦e₂′ (where e₁′ is typically less than zero while e₂′ isgreater than zero). Nonconforming, post-trim wafers may have to bethrown away. In the above, exemplary process where L2 is about 0.140 μm,e₁′ may be −0.015 μm for example while e₂′ may be+0.01 μm.

[0047] During mass-production, a situation may arise (as already alludedto above) where relatively large numbers of wafers begin to slip outsidethe predefined, allowed tolerance-range, e₁′≦e_(GatepR)≦e₂′. In otherwords, the measured critical dimension values begin to slip away fromclosely matching the target, L_(1T) or L_(2T), value. This couldindicate that some parameter of the PR-development process might beslipping and that it may be desirable to fine-tune the PR-trimmingprocess in order to compensate for the slippage. On the other hand, itcould be a random statistical coincidence.

[0048] The safest parameter to play with (if any process parameter is tobe tuned at all) is the isotropic etch time which converts pre-trimfeature 119 into post-trim feature 118. FIG. 2 illustrates a plot oftrim-distance (etch. depth) versus trim-time for a well-defined(well-characterized), first trim process 205. Under normalcircumstances, with the PR etch time set at the nominal value, say t₀,the average ADICD₁ measurement of the pre-trim PR features 119 shouldcome back with a measured feature length of L_(M) being very close orequal to the target length, L_(1T) (that is, L_(M)=L_(1T)). Thecorresponding, next PR trim time that will be used to convert a next,on-target, pre-trim feature 119 to an on-target, post-trim feature 118having target length, L_(2T) will be the same PR trim time of t₀ as isindicated in FIG. 2 by the notation, Next=t₀.

[0049] However, sometimes the measured feature length, L_(1M) ofmetrology step 121 can be measurably, but not substantially, below thetargeted etch length, L_(1T), such as indicated in the drawing byL_(Ma)=L_(1T)−_(A), where Δ_(A) is a relatively small, but still out oftolerance, positive perturbation. As one or more wafers begin to exhibitthe new measured length, L_(Ma), the PR trim process may be predictablyfine-tuned by decreasing the PR trim time slightly as indicated on thetime line by the notation Next=t₀−Δ₁. PR trim distance should thendecrease slightly as predicted by the well-defined, distance versus timecurve 205 and this should bring the post-trim feature length, L₂ of suchwafers back into the allowed tolerance-range, e₁′≦e_(GatePR)≦e₂′. Inother words, after such fine tuning, the average ADICD₂ should again bevery close to or exactly equal to the target length, L_(2T).

[0050] It should be noted in passing that, although the immediatelyabove and below discussions assume that the ADICD₁ metrology step (121)is being used to control the PR trim time on a feed-forward basis, it ispossible to alternatively or additionally use the ADICD₂ metrology step(122) for controlling the PR trim time on a feed-back basis. Anadvantage of using the described, feed-forward approach (wherein theADICD₁ metrology step, 121 controls PR trim time of same product) isthat over-etched product (samples where L1 is below target) do not haveto be discarded. In counter to this, an advantage of using the feed-backapproach (wherein the ADICD₂ metrology step, 122 controls the PR trimtime for subsequent product) is that a tighter control over dimensionsmay be obtained because actual results, after PR trim, are beingmeasured instead of relying on pre-trim measurements. The feedforwardcontrol system (which relies on 121 for controlling PR trim time) is anopen-loop and thus predictive approach. However, a disadvantage of usingthe feed-back approach (where ADICD₂ controls PR trim time), at least inconventional processes, is that over-trimmed product (samples where L2is below target value L_(2T)) have to be discarded because one cannotun-do an excessive trim. One can only further trim, a still-undertrimmedfeature. The present invention contemplates using either approach or acombination of both.

[0051] Continuing with the explanation of FIG. 2, if the measuredfeature length, L_(M) of a significant number of wafers begins to sliptowards a new mean that is above the allowed tolerance-range,e₁′≦e_(GatePR)≦e₂′, but not substantially above the target length, suchas indicated by L_(Mb)=L_(1T)+Δ_(B), where AB is a relatively small andpositive perturbation, then the ensuing PR trim time may beautomatically fine-tuned as indicated on the time line by Next=t₀+Δ₂,where Δ₂ is positive. After such fine tuning, the post-trim, ADICD₂value (L2) should return to being again very close to or exactly equalto the target post-trim length, L_(2T).

[0052] Let's say, however, that at some point in time the measured,pre-trim length values, L_(M) start coming in as being drasticallylarger than the target length, such as indicated by L_(Mc)=L_(1T)+Δ_(C),where Δ_(C) is a relatively much larger, positive deviation than areeach of the fine-tunable deviations represented by Δ_(A) and Δ_(B). Insuch a case, curve 205 may no longer provide an accurate prediction forwhat results are to be expected under the current state of the PRtrimming equipment. If PR trim time is changed dramatically, the processcan become highly nonlinear. In other words, if users begin to push theprocess outside the linearly predictive part of curve 205, the actualresults may not conform with what the curve 205 predicts. There may beno well-defined amount of increase in trim time (e.g., Next=t₀+Δ₃; notshown) that can assuredly return production results back to the desired,mean target value, L_(2T) when the L_(Mc)=L_(1T)+Δ_(C) situation isencountered. Alternatively, the curve-dictated increase in trim time(e.g., Next=t₀+Δ₃) may be too large to be acceptable for meetingproduction schedules.

[0053] Process technicians may elect in such a situation to switch to adifferent PR trim process such as second process 207. However, thesecond trim process 207 may be one that has not been well characterized.Its results may therefore not be accurately predictable. This may throwautomated control out of a stable region of operation. Also, if the newprocess 207 is a more energetic one than the better-defined, process205, fabrication uniformity may change drastically by shifting to themore energetic process 207. Nonetheless, this is something that issometimes done in order to meet production schedules.

[0054] Human technicians may well make correct, non-automated decisionsin the short run. However, experience shows that over the long haul,process technicians will eventually make a human judgment error andchoose a wrong one of a set of poorly-defined trim processes such as207. Yields may then suffer drastically and thereby bring about anoutcome that is the exact opposite of what the technicians wanted,namely to minimize process error.

[0055] There is need for a better approach. Preferably this betterapproach is one that is automated so that human judgment error does notparticipate as a controlling factor.

[0056] The above discussions concerning the tuning of PR trim time inresponse to ADICD measurements is just an introduction to a problem ofbigger scope. That scope will be expanded on, shortly. However, beforewe continue along that path, it is worthwhile to understand theremainder of a transistor-forming process that conforms with the presentinvention. FIG. 1B shows a cross-sectional view of a subsequent,transistor-precursor structure 120 that is derived from structure 100(FIG. 1A). In the time frame of FIG. 1B, the trimmed PR block 118 hasbeen used as an initial mask for etching ARC layer 116 to thereby definea hard mask region 126. Subsequent anisotropic etching has produced thepost-etch, polysilicon gate structure 124, as shown. This gate structure124 has a length L2′ which should be equal to or relatively close to acorresponding and pre-defined, post-etch target length L_(2′T) if theanisotropic etch has proceeded in a predicted manner. One way that theL2′ dimension can be made to statistically track the pre-defined, targetlength L_(2′T) is by using the PR trim tuning method shown in FIG. 2 andby throwing away those nonconforming wafers that cannot be correctedwith just the use of PR trim tuning. In other words, we discard those ofthe pre-trim or post-trim wafers whose respective ADICD₁ or ADICD₂ erroris outside the fine-tunable range, e₁′≦e_(GatePR)≧e₂′.

[0057] Similar to the way that samples of the first transistor-precursorstructure 100 were sent to the first and/or second metrology stations(121 and 122 respectively); and similar to the way that nonconforming,unreworkable wafers were discarded; samples of the secondtransistor-precursor structure 120 are typically sent to a thirdmetrology station 123. This third metrology station 123 may be dedicatedto optically measuring the L2′ dimension of gate sub-structure 124. Adetermination is made of the average per-wafer and/or per wafer-lotvalues of the post-etch, length dimension, L2′ and of its statisticaldistribution at various points of the post-etch wafers (e.g., a 9-pointstar test) and across the respective production lot. Such measurementand calculation steps are sometimes referred to as FICD (FinalInspection measurement of Critical Dimension). As with the case ofADICD, an allowed tolerance-range, e₃≦e_(Gate)≦e₄ is defined for theFICD results. Nonconforming, post-etch wafers are thrown away.Variations in L2′ due to mask undercutting (if there is any) can becompensated for in a manner similar to that explained for FIG. 2.Feedback control from the FICD measurement step 123 can be used tofurther tweak the PR trim time (t_(Next′)=t_(Next)±Δ=t₀±Δ_(1/2)±Δ_(3/4))of FIG. 2.

[0058]FIG. 1C shows a cross-sectional view of a subsequent, thirdtransistor-precursor structure 130 derived from in-process structure 120(FIG. 1B). Here, a film has been deposited with a film thickness ofF_(w). The film may be composed of a spacer material such as an oxide oran oxynitride and it is typically, conformably deposited as layer 132over the top and sides of the etched gate structure 124. Depositionthickness, F_(w), is a controllable variable whose value is predictivelyset prior to the actual deposition. As with all mass-productionoperations, the actual deposition thickness may vary from the targetthickness on a sample by sample basis. The total lateral length of gatestructure 124 plus the sidewall portions of film 132 is denoted as L3.

[0059]FIG. 1D shows a subsequent, fourth transistor-precursor structure(product-in-process form) 140 derived from in-process structure 130.Here, the initial spacer material film 132 has been anisotropicallyetched-down to remove its laterally-extending portions Thevertically-extending portions of the spacer material remain and therebydefine, a set of trimmed spacer sidewalls 144 along the sides of gatesub-structure 124. The overall length of gate 124 and the trimmedspacers 144 is denoted as L3′. The post-trim width of each of thesidewall spacers is denoted as S_(w). The term “trimmed” as applied hereto the spacer sidewalls 144 is understood to encompass a fine-tuningadjustment to one or both of the initially-set, deposition thickness,F_(w) (FIG. 1C) and to the anisotropic etch time (FIG. 1D). Fine-tuningof the spacer sidewall thickness is preferably controlled primarily withfine-tuning of the initial deposition thickness, F_(W) because this iseasier and less costly to control than modifying the anisotropic etchthat leaves behind the spacer side-walls 144. However, it is within thecontemplation of the present invention use either one or a combinationof both the initial deposition thickness (F_(W)) and the side-wall trimas process variables that may be fine-tuned.

[0060] After the spacer formation and trimming process is completed,samples of the fourth transistor-precursor structure 140 are sent to afourth metrology station 125. This fourth metrology station 125 may bededicated to optically measuring the thickness dimension, S_(wM) of eachof sidewalls 144. A determination is made of the average per-waferand/or per wafer-lot values of the measured, post-etch, measuredsidewall thickness dimension, S_(wM) and of its statistical distributionat various points of the post-etch wafers (e.g., by way of a 9 pointstar test) and across the respective production lot. As with the case ofthe ADICD and/or FICD measurements, an allowed mass-productiontolerance-range, e₅≦e_(Sidewall)≦e₆ is for the S_(wM) results, wheree_(Sidewall)=S_(wM)−S_(wT) and S_(wT) is a predefined target value aboutwhich the measurements should closely center and e₅ is typically lessthan zero while e₆ is greater than zero. Nonconforming, post-etch wafersmay be thrown away if over-etched, or returned for further etching(re-work) if under-etched. Although the measured sidewall thicknessdimension, S_(wM) is preferably defined by measurements taken afterdeposition layer 132 is trimmed, it is within the contemplation of theinvention to define the measured sidewall thickness dimension, S_(wM) asbeing determined instead by measuring the pre-trim thickness F_(W) ofdeposition layer 132 or as being determined by combining pre-trim andpost trim measurements for the sidewalls 144 as may be appropriate.

[0061] Variations over time in the returned values of S_(wM) due toprocess slip (if there is any) can be compensated for in a mannersimilar to that explained for FIG. 2, but this time, preferably usingthe initial deposition thickness, F_(w) as a feedback, tuning control.Alternatively, or additionally, the post deposition trim time for thesidewalls may be tuned.

[0062]FIG. 1E shows a next state 150 of the in-process structure whereinTilted Channel Implant (TCI) is performed to thereby define a gradient(P, P′, P″) of channel doping density within regions where source anddrain regions will abut into transistor channel regions. The PNjunctions that will form between the channel and the source/drainregions, will be defined later. The characteristics of these PNjunctions (including depth and lateral position) will be determined inpart by the locus of the TCI-created, channel doping. More specifically,after thermal diffusion, there will be points inside the substrate wherethe TCI-created, density of P dopants balances equally against thesource/drain doping density of implanted N dopants. In other words thepoints that satisfy N=P in terms of doping density will define theneutral center of the PN junction as shown at 157 in FIG. 1F).

[0063] The Tilted Channel Implant (TCI) may be carried out by aimingimplant beams at a tilted angle towards the combined gate structure 124and trimmed sidewall spacers 144. The TCI process may also be masked byan added, photoresist mask 145. FIG. 1E shows a TCI doping source 152applying tilted ion beams such as 153 and 154 to the structure. It isunderstood that the TCI implant operation will usually rotate either insteps or uniformly about the Z axis (vertical axis). In one embodiment,the rotations are in equal steps of between 45 degrees to 90 degreesthereby respectively providing between 8 to 4 equal rotations. Theuniform or stepped rotations provide a generally uniform distribution ofdopants in areas that are not shaded by features such as gate 124 andits sidewalls 144 (or mask 145). It is known in the art that a so-called‘halo effect’ will develop in the shaded regions of the gate 124 andsidewalls 144. At a relatively large lateral distance out and away fromthe center of the spacer/gate/spacer structure 144/124/144, the dopantimplant concentration will be relatively large (P) due to symmetricalcontribution by unshaded beams such as 153 from all angles. Atrelatively smaller lateral distances from the center of structure144/124/144, the implant concentration will be relatively moderate (P′)due to some shadowing effect being provided by the upwardly projecting,gate/sidewalls structure 124/144. At yet a smaller lateral distance, theion doping contribution will be relatively even smaller (p″) andshallower because the only ion beams that manage to get to suchunder-the-gate locations are those tilted beams such as 154 which passthrough a lower portion of sidewall 144. Sidewall 144 behaves as sort ofa soft sponge that absorbs some of the ions and reduces the energy, andthus reduces the density and the depth of penetration of those ions (P″)that get through.

[0064] As for the channel doping that will develop under the center ofgate/sidewalls structure 144/124/144, the gate structure 124 may act asa hard mask that blocks substantially all or part of the TCI dopingbeams 153-154 from getting through to the underlying, middle part of thechannel region. Such a partial or full shading effect may leave thecentral part of the channel with essentially only the initial, P-density that was present in the initial substrate. (Of course, dopingsuperposition variations on this basic approach are within thecontemplation of the invention.) From the above it is seen that ahalo-effect doping gradient may be produced in the channel. Under thevery center of the gate/sidewalls structure 144/124/144, the ion dopingcontribution by the TCI operation will be essentially absent and theroughly middle part of the channel will thus retain the initial P-concentration that it had before the TCI operation (or a superpositionof such with other doping processes). In one embodiment, the initial, P-density is about 1E15 (or 10¹⁵) doping atoms per cm³ while the heavier Pdensity that is provided by the TCI operation is about 1E18/cm³. Theheavier P density tapers down through successive intermediate levels, P′and P″ down to the lower P-density as one moves laterally from outsideand toward the center of the shadow cast by the spacer/gate/spacerstructure 144/124/144. This halo-distributed, channel doping gradient isrepresented schematically at 155 in FIG. 1E.

[0065] N-type dopants for forming the source/drain regions may beimplanted before and/or after the Tilted Channel Implant 153/154. In oneembodiment, a shallow, first N implant is performed before sidewalls 144are formed to thereby define a shallow, inner part 156 a of thesource/drain regions 156/156′. In the same embodiment, a deeper, secondN implant is performed after sidewalls 144 are formed to thereby definea deeper, outer part 156b of the source/drain regions. Typically, thegate structure 124 will acquire a heavy N+ doping from the ions itintercepts during the source/drain dopant implants. The top of the gatestructure 124 may be masked (not shown) during the TCI operation.

[0066] A schematic of the resulting source and/or drain profiles isshown at 156 and 156′ of FIG. 1F. The PN junction 157 that outlines theprofile is understood to be the locus of points in which P-type dopingbalances out with N-type doping. The locations of such P=N balancepoints can be shifted inwardly (towards the center of spacer/gate/spacerstructure 144/124/144) or outwardly depending on how the P″P′P gradient155 is shaped and located and depending on how the N-type source/drainimplants are carried out and how all dopants are diffused by thermalprocess.

[0067] The illustrated source and drain regions 156 and 156′ in FIG. 1Fprovide an effective channel length, L_(eff) therebetween. The dimensionof this effective channel length, L_(eff) is a function of both the TCIprocess and the N-type source/drain implants and a subsequent thermalannealing process that diffuses the implanted ions according topredefined diffusion characteristics.

[0068] There may be a slight overlap L_(ov) between the outer verticalwalls of the gate 124 and the ends of the source and drain regions. Thisoverlap defines an undesirable parasitic capacitance known as C_(ov).During rapid switching of gate-to-source voltage, V_(GS), the parasiticcapacitance, C_(ov) needs to be charged or discharged in order to bringthe effective gate-to-source voltage above or below the transistor'sthreshold level, V_(T). In general, large values for the parasiticcapacitance, C_(ov) are undesirable because they tend to slow downswitching speed and/or increase power consumption.

[0069] In summary, it is seen from the illustrated sequential processsteps of FIGS. 1A-1E how certain critical dimensions such as,L₂′+S_(w)=L3′, may determine the ultimate effective length L_(eff) ofthe transistor. It is understood in the art that L_(eff) is critical todefining many parameters of transistor behavior including switchingspeed and the transistor's threshold voltage, V_(T). The profile anddoping concentration gradients in regions 155 and 156 a/b are alsoresponsible for defining threshold voltage V_(T). The total amount ofcharge that may be stored in the surface region of the channel isdetermined by the net density of P-type doping atoms provided in thisregion and by the surface-length limiting effects of the source anddrain regions 156/156′ which have a countering amount of net N-typedoping atoms provided therein.

[0070]FIG. 3 shows an automated fabrication system 300 in accordancewith the invention. Fabrication system 300 includes one or more datacollecting computers 301 that collect and thereafter optionallytransform (via computational steps) process-related data, includingmetrology data that defines measured values, L₂M and SwM orcorresponding other measured values relating to gate length and sidewallthickness.

[0071] Fabrication system 300 further includes one or more process flowcontrol computers 302 that track in-process wafers and define thetargeted process dimensions or other attributes that are to be impartedto the wafers during different parts of the fabrication flow sequence.The process flow control computer(s) 302 therefore generally define thetarget values, L_(2T) and S_(wT) or corresponding other target valuesrelating to gate length and sidewall thickness.

[0072] Fabrication system 300 yet further includes one or more implantcontrol computers 303 that communicate with one or both of the processflow control computer(s) 302 and the data collecting/processingcomputer(s) 301. Computer(s) 301 and 302 are usually interlinked withone another as well as with implant control computer(s) 303 by way of acommunications network.

[0073] A fabrication control process 360, that will be shortlydescribed, may be implemented by way of software and/or hardware eitherfully in one, or distributively among, computers 301, 302 and 303. It iswithin the contemplation of the invention to use general-purpose, and/orspecial-purpose computers that are re-configured or programmed withappropriate software to perform the herein-described functions. There-configuring or programming of the computer(s) may be carried with useof one or both of computer-readable media (e.g., a CD-ROM or floppydiskette) 305 and network-downloaded signals 306, where the media 305and/or signals 306 convey software instructions to respectively targetedcomputing machines for causing any one or more of such computer(s)301-303 to become configured or programmed to perform part or all of theTCI feedforward control operations (360) described herein.

[0074] As shown, fabrication system 300 comprises a variable TCI beamsource 352 that is operatively and automatically controlled by implantcontrol computer(s) 303. The variable TCI beam source 352 has at leastone, and preferably both of variable energy and variable dosagecapabilities. The variable energy and dosage controls of source 352 aredenoted as Energy_(a) and Dose_(b) and these are controllable by implantcontrol computer(s) 303. Signals 362 and 364 that respectively representmanufacturing tolerance errors in gate length (e_(Gate)) and sidewallthickness (e_(Sw)) are fed forward from their respective calculatingmeans (361, 363) to the TCI control computer(s) 303. In one embodiment,e_(Gate) is defined as target length L_(2T) (which could be either thePR trim target length or the post-etch gate target length or acombination of both) minus the measured PR length L₂M (which could beeither DICD or FICD or a combination of both). In the same or analternate embodiment, e_(Sw) is defined as measured sidewall thicknessS_(wM) minus target thickness S_(wT). The measured values can bedirectly measured ones or values that are derived as statistically fairrepresentatives of what is happening in their respective PR-trimming,gate-etching or sidewall film-deposition or sidewall etching/trimmingprocesses.

[0075] The energy and/or dosage values used in the TCI process (352) aremanually or automatically adjusted for each respective product inresponse to the received one or both of error signals 362 (e_(Gate)) and364 (e_(Sw)). The preferred modality is for automatic(machine-implemented) adjustment because that removes the possibility ofhuman error from the process. The energy and/or dosage values provideadditional controllable variables which can be automatically tuned inaccordance with the invention to counter manufacturing tolerance errorsas will be explained shortly. Such feed forward means may be used inaccordance with the invention for improving mass-production statisticaldistribution of critical parameters in semiconductor devices.

[0076] Consider first the case where error signals 362 (e_(Gate)) and364 (e_(Sw)) are both zero. For this case, there will be a specific andpredefined set of default values (experimentally pre-established) forcontrollable variables, Energy_(a) and Dose_(b) of source 352 as are tobe applied for a respective product (e.g., a microprocessor chip or amemory chip). Let us call these, E₀ and D₀ respectively. Source/drainregion 356 will have a corresponding, first doping distribution profileas represented by first junction outline 356 a. It is understood thatrepeated electrical testing of final product statistics in themass-production line has been performed beforehand to demonstrate thatthe default energy and dosage values, E₀ and D₀ are the essentiallyoptimal ones for the given product in the case where the measured ADICD,FICD and sidewall thickness values are essentially on target.

[0077] Consider next the case where error signal 364 (e_(Sw)) ispositive while signal 362 (e_(Gate)) is zero. That implies that themeasured sidewall thickness S_(wM) is greater than the desired (target)thickness. If the TCI doping operation continues to use the defaultenergy and dosage values, E₀ and D₀, the measurement-detected, excessthickness of the sidewall 144 will effectively pull the P-P′-P″ outline355 laterally outward, away from the center of the gate. Because ofthis, the outline of doping profile 356 will also shift laterally backfrom ideal position 356 a to a further-back position 356 b on each sideof the gate. That works to undesirably increase L_(eff).

[0078] Suppose, however that we now increase controllable variableEnergy_(a) to a value greater than the default dosage value, E₀. Theamount of increase can be adjusted to push the P-P′-P″ outline 355deeper into the substrate so the outline 355 essentially returns to itsideal position. As a result, PN junction outline 356 b is also pusheddeeper into the substrate so the PN junction outline essentially returnsto the ideal outline position 356 a. L_(eff) is then decreased back toits ideal value and mass-production may continue without suffering fromthe ill effects that the positive sidewall error (364) would haveotherwise caused.

[0079] In one embodiment, the amount of adjustment of fine tuning to theTCI energy value is automated and given by a linear or quasi-linearinterpolation equation of the following form:

Energy_(a) =E ₀*(1+βe _(Sw) /S _(wT))  {Eq. 2}.

[0080] In the above equation, Eq. 2, the multiplying factor, β mayeither be a constant or a function of a prespecified windowing range ofthe normalized error, e_(Sw)/S_(wT). In one embodiment, where P-channeldevices (PNP FET's) are being fabricated, the multiplying factor, β isdefined as one or more constant values selected from the range,0.02≦β≦0.20 where the selected value or values may depend on the signand/or magnitude of e_(Sw)/S_(wT). In a second embodiment, where againP-channel devices are being fabricated, the multiplying factor, β isdefined as one or more values selected from the range, 0.05≦β≦0.15 wherethe selected value depends on the sign of e_(Sw)/S_(wT).

[0081] The multiplying factor, β may be derived from an empiricalexperience curve 450 such as shown in FIG. 4A which has one, two, ormore empirically-obtained prediction points (e.g., E_(H), E_(L)). Testsmay be conducted to discover at least one, higher level of implantenergy, E_(H) which is statistically significant and useful for bringingelectrical characteristics of manufactured devices back to the targetedcharacteristics in cases where the measured side wall thickness, S_(wM)is larger than the desired or target thickness S_(wT) by a given amount.For example, if the targeted thickness for the side walls is 400 Å inorder to achieve the desired targeted electrical characteristics, aplurality of experiments may reveal that higher implant energy level,E_(H) is useful for achieving the same electrical characteristics incases where the side wall thickness is found by measurement to be thehigher value of say S_(wMH)=600 Å. Such experiments and empiricalfindings may be carried out for a number of different points onexperience curve 450. Then, one or more linear, or other kinds ofinterpolations may be used for calculating to an appropriately-closelevel of approximation, the desired higher energy levels for otheramounts of positive thickness error, e_(Sw). Straight line 451 in themagnified explosion, for example, shows how one such linearinterpolation may be carried out for errors that lie between theexperimentally-validated values for energy levels in the windowing rangeof E₀ to E_(H) or above.

[0082] Returning to FIG. 3, suppose now that the sidewall error signal,e_(Sw) (364) is negative, thereby indicating that the measured sidewallthickness is less than the target or desired sidewall thickness. If thisis so, the nominal implant energy E₀ will be too high and will push theTCI doping implant P-P′-P″ 355 too deep into the substrate. As aconsequence, the resulting PN junction profile 356 c will be too deep.The solution, in accordance with the invention, is to reduce the implantenergy level to a lower value such as, E_(L). Again, the experiencecurve 450 is used to validate with empirical measurements what one ormore values of lower implant energy such as E_(L) reproduce theelectrical characteristics that are also found in devices whose sidewallthickness is at the nominal or targeted value of S_(wT). Straight line452 in the magnification explosion shows how linear interpolation may beused to calculate a substantially close approximation of the correctionvalues for the implant energy in cases where the error is other thanthose which are validated with corresponding experiments. Note thatdifferent slopes can appear for the linear interpolation lines, 451 and452 that extend from the ideal or default point, (E₀, S_(wT)).Accordingly, the sign of the eSw error signal (364) may be used as awindowing parameter to determine which of interpolation lines, 451 and452 is to be used. Other windowing determinants may be used additionallyor alternatively as various situations may dictate. The multiplyingfactor, β of Eq. 2 may therefore be kept as a positive value whosemagnitude changes in response to the sign of the e_(Sw) error signal.The sign of the e_(Sw) error signal determines automatically whether theTCI implant energy, E_(a) is to be increased or decreased in accordancewith one embodiment of the above explanation.

[0083] Referring again to FIG. 3, consider now a case where the measuredgate length L_(2M) is smaller than the desired or targeted length L_(2T)even though the sidewall thickness is on target (e_(Sw)=0). The depth ofthe TCI process will be accurate relative to the sidewall edges of thegate 124. However, the effective gate length, L_(eff) of the transistorwill be too short. To counter this effect, the dosage Dose_(b) of theTilted Channel Implant should be increased to thereby effectively pushthe location of the P-P′-P″ outline 355 laterally out and away from thecenter of the gate 124. The effect of this will be to also push the P=Njunction 356 a laterally outward so that the desired effective gatelength, L_(eff) is realized even though the gate dimension, L_(2M) wasbelow target (L_(2M)<L_(2T)).

[0084] In one embodiment, the following, interpolating correctionformula (Eq. 3) is used:

Dose_(a)=Dose₀*(1+α((L_(2T)−L_(2M))/L_(2T))  {Eq. 3}

[0085] Multiplying factor α is positive and causes the actual TCI dosageto increase above ideal value, Dose₀ if L_(2M) is found to be belowtarget (L_(2M)<L_(2T)). On the other hand, if L_(2M) is found to beabove its target value (L_(2M)>L_(2T)), then the action of a controlmechanism acting according Eq. 3 will be to decrease the actual TCIdosage to a value less than the ideal value, Dose₀. This will work topull the P=N junction 356 a laterally inward so that the desiredeffective gate length, L_(eff) is realized even though the gatedimension, L_(2M) was above target (L_(2M)>L_(2T)).

[0086] In one embodiment, where P-channel devices (PNP FET's) are beingfabricated, the Eq. 3 multiplying factor, α is defined as one or moreconstant values selected from the range, 0.05≦α≦0.15 where the selectedvalue or values may depend on the sign and/or windowed magnitude ofe_(Gate)/L_(2T). In a second embodiment, where again P-channel devicesare being fabricated, the Eq. 3 multiplying factor, a is defined as oneor more values selected about the range of α being approximately 0.10,where the selected value depends on the sign and/or magnitude ofe_(Gate)/L_(2T).

[0087] The Eq. 3 multiplying factor, α may be derived from an experiencecurve 460 such as shown in FIG. 4B. Tests should be conducted todiscover what higher or lower level of implant dosage, Dose_(a) isstatistically significant and useful for bringing electricalcharacteristics of manufactured devices back to the targetedcharacteristics in cases where the measured gate length dimension,L_(2M) is different from the desired or target length, L_(2T) by arespectively given amount. For example, if the targeted thickness forthe gate 124 is L_(2T), a desired or targeted electrical characteristicof the transistor such as threshold voltage, V_(TT) may be predefined,where the latter is associated with a corresponding channel surfacecharge Q_(TT). A plurality of experiments may reveal that higher implantdose level, D_(H) is useful for achieving the same electricalcharacteristics in cases where the gate length, L_(2Ma) is found bymeasurement to be lower than the targeted length, L_(2T) by a givenamount. The comparatively higher TCI dosage, D_(H) brings the netsurface charge in the channel back to target level, Q_(TT). Suchexperiments and empirical findings may be carried out for a number ofdifferent points on experience curve 460. Then, one or more linearinterpolations may be used for calculating the desired higher energylevels for other amounts of positive gate length error,e_(Gate)=L_(2T)−L_(2M). Straight lines such as 451 in the magnifiedexplosion of earlier FIG. 4A may be used to provide interpolation forerrors that lie between the experimentally-validated values for Dosagelevels D₀ and D_(H).

[0088] Similarly, if the gate length error, e_(Gate)=L_(2T)−L_(2M) isinstead negative, thereby indicating that the measured length is greaterthan the target length, lower TCI dosage such as D_(L) may be found byway of experimental validation to be the amount that brings net channelcharge (and thus V_(Thresh)) to the target value (Q_(TT) or V_(TT)respectively). Again, straight lines such as 452 in the magnifiedexplosion of earlier FIG. 4A may be used to provide interpolation forerrors that lie between the experimentally-validated values for Dosagelevels D₀ and D_(L).

[0089] The characterizing curve for the electrical characteristic thatis being controlled (e.g., V_(Thresh)) does not have to be monotonicallyrising such as shown by exemplary curve 460. It may instead behump-shaped such as shown by exemplary curve 470 or even more complex.The Eq. 3 multiplying factor, α should of course be selected accordingto the nature of the characterizing curve, 460 or 470 rather than justblindly according to whether the gate length error,e_(Gate)=L_(2T)−L_(2M) is positive or negative. Windowing determinatorsmay be used to select the correct linear, or other interpolatingequation for each respective section of an experience curve such as 460or 470.

[0090] FIGS. 5A-5B provide a process flow chart for a manually and/ormachine-implemented process 500 that includes the carrying out of TCIfeedforward correction in accordance with the invention. It is presumedthat, without the presence of such TCI feedforward correction, thatthere will be certain, not-yet-expanded and respective, ranges ofallowed error for one or more of the PR trim processes (see FIG. 1A),for the gate layer etch (see FIG. 1B), for the sidewall depositionprocess (see FIG. 1C), and for the sidewall etch/trim processes (seeFIG. 1D). Embodiments in accordance with the invention do notnecessarily carry out all of the steps or expansions of respective,ranges of allowed error as described in the following. It is illustratedby way of respective operations 510, 520, 530 and 540, that respectivetolerable errors can be expanded somewhat for one or more of the PR trimprocesses (steps 512-514), for the gate layer etch processes (steps522-524), for the sidewall deposition process (steps 532-534), and forthe sidewall etch/trim processes (steps 542-544) because of the countercompensating adjustments that are made to TCI energy and/or dosage inthe more downstream step 552. The respective expansions of tolerableerror range for each of the out-of-range error tests in FIGS. 5A-5B,namely for tests 514, 524, 534 and 544, can mean that more wafers passeach such test and ultimate yield increases as compared to a likeprocess that does not have feedforward compensation in the TCI step. Itis therefore the feedforward compensation in TCI adjustment step 550that allows the expansion of the error ranges and the increased yield ofwithin-specification devices.

[0091] More specifically, in the first and optional, error rangeexpansion step 510, a comparatively expanded error range,e₁″≦e_(GatepR)≦e₂″ is established where e₁″<e₁″ and/or e₂″>e₂″ and wheree₁′ and e₂′ are the error limits used (typically the first one beingnegative and the second positive) if TCI feedforward adjustment step 550is bypassed. Next, in step 512, the photoresist (PR) patterning andtrimming processes are performed and a corresponding DICD₁ and/or DICD₂measurement is taken. See FIG. 1A.

[0092] In test step 514, it is determined whether one or more of theADICD errors is outside of its respective and allowed tolerance range.If the answer is YES, then the out-of-range wafer (or lot of wafers) maybe discarded as indicated by step 517. Optional decision step 516 can becarried out for cases where it is economically and technically feasibleto strip the out-of-specification PR layer (118 or 119) and form a newone in its place. In step 516, the reason for the out-of-range result ofstep 514 is analyzed and a decision is made whether to re-tune the PRpatterning and/or trimming process and to thereafter or nonethelessstrip and rework the nonconforming wafers.

[0093] Path 515 is taken by wafers that are found to be in-range by test514. In optional, error range expansion step 520, a comparativelyexpanded, second error range, e₃″≦e_(GateEtched)(Poly)≦e₄− isestablished for gate layer etching, where e₃″<e₃′ and/or e₄ ″>e₄′ andwhere e₃′ and e₄′ are the error limits used (typically the first onebeing negative and the second positive) if TCI feedforward adjustmentstep 550 is bypassed. Next, in step 522, the gate layer etchingprocesses are performed and a corresponding FICD measurement is taken.See FIG. 1B.

[0094] In test step 524, it is determined whether one or more of theFICD errors is outside of its respective and allowed tolerance range. Ifthe answer is YES, then the out-of-range wafer (or lot of wafers) may bediscarded as indicated by step 527. Optional decision step 526 can becarried out for cases where it is economically and technically feasibleto further etch wafers whose gate layer is not yet etched far enough(under-etched). In step 526, the reason for the out-of-range result ofstep 514 is analyzed and a decision is made whether to re-tune the PRpatterning and/or trimming process and to thereafter or nonethelessfurther etch (528) those wafers or dice whose gate layer isunder-etched. (It is generally not feasible or economical to strip andrework nonconforming wafers whose gate layer is over-etched such thatgate length is too short.)

[0095] Path 525 is taken by wafers that are found to be in-range by test524. In optional, error range expansion step 530, a comparativelyexpanded, third error range, e₅″≦e_(Depo)≦e₆″ is established forsidewall layer deposition, where e₅″<e₅′ and/or e₆″>e₆′ and where e₅′and e₆′ are the error limits used (typically the first one beingnegative and the second positive) if TCI feedforward adjustment step 550is bypassed. Next, in step 532, the depositing of the sidewall layer(132) is carried out and a corresponding deposition thicknessmeasurement is taken. See FIG. 1C.

[0096] In test step 534, it is determined whether one or more of thedeposition thickness errors is outside of its respective and allowedtolerance range. If the answer is YES, then the out-of-range wafer (orlot of wafers) may be discarded as indicated by step 537. Optionaldecision step 536 can be carried out for cases where it is economicallyand technically feasible to further etch wafers whose sidewalldeposition thickness is too large for correction simply with thesidewall etch/trim process 542. In step 536, the reason for theout-of-range result of step 534 is analyzed and a decision is madewhether to re-tune the sidewall material deposition process and tothereafter or nonetheless further etch (538) those wafers whose sidewalllayer 132 is too thick. (It is generally not feasible or economical tostrip and rework nonconforming wafers whose sidewall deposition layer istoo thin for counter compensation in the subsequent, sidewall etch/trimprocess 542.)

[0097] Path 535 is taken by wafers that are found to be in-range by test534. Additional wafers may reach next step 540 or 542 after beingcorrected in step 538. In optional, error range expansion step 540, acomparatively expanded, fourth error range, e₇″≦e_(SW—)trim≦e₈″ isestablished for sidewall etching and trimming, where e₇″<e₇′ and/ore₈″>e₈′ and where e₇′ and e₈′ are the error limits used (typically thefirst one being negative and the second positive) if TCI feedforwardadjustment step 550 is bypassed. Next, in step 542, the anisotropicetching and/or subsequent isotropic trimming of the sidewall spacers(144) is carried out and a corresponding sidewall thickness measurement(S_(wM)) is taken. See FIG. 1D. The trimming of the sidewall spacers(144) compensates partially for error in the sidewall depositionthickness.

[0098] In test step 544, it is determined whether one or more of thesidewall thickness errors is outside of its respective and allowedtolerance range. If the answer is YES, then the out-of-range wafer (orlot of wafers) may be discarded as indicated by step 5437. Optionaldecision step 546 can be carried out for cases where it is economicallyand technically feasible to further etch wafers whose sidewall post-trimthickness is too large. In step 546, the reason for the out-of-rangeresult of step 544 is analyzed and a decision is made whether to re-tunethe sidewall trim process and to thereafter or nonetheless further etch(548) those wafers whose sidewall thickness is too large. (It isgenerally not feasible or economical to strip and rework nonconformingwafers whose sidewall spacers are too thin for counter compensation inthe subsequent, TCI process 552.)

[0099] Path 545 is taken by wafers that are found to be in-range bysidewall thickness test 544. In following step 550, the TCI energyand/or dosage values are adjusted in response to sidewall thicknesserror (Energy_(a)=f(e_(Sw)) . . . {Eq. 2a}) and in response to gatelength error (Dose_(a)=f(L_(2T)−L_(2M)) . . . {Eq. 3a}) per the abovedescribed considerations. In step 552 the TCI doping operation iscarried out in accordance with the adjusted energy and/or dosage valuesof step 550. Continuation flow 555 represents the carrying out offurther, downstream processes after the TCI operation 552. Sampled,electrical characterization of devices that are mass-produced by processflow 500 may be carried out as part of the downstream continuation 555.

[0100] Table 1 demonstrates computer simulation results for electricalcharacterization of a given product device that is simulated to bemass-produced by different variations of process flow 500 and assumed tohave Gaussian distributions of error in the various critical dimensionsdiscussed above. TABLE 1 FF TCI FF TCI Conven- Correct Correct ElectricNo tional using using Param APC APC FICD DICD I_(on) 0.76 0.58 0.46 0.46I_(off Leak) 0.50 0.39 0.38 0.37 C_(OV) 0.51 0.69 0.38 0.38

[0101] In Table 1, the horizontal rows respectively represent the 3 σmean values for power consumption in terms of transistorconductive-state current, leakage current and overlap capacitance. Thevertical columns respectively represent, in left to right order, thestatistical results for simulation with no Automatic Process Correctionof any kind (sidewall trim or TCI), conventional Automatic ProcessCorrection (no TCI adjust, but yes with respect to sidewall trim), TCIfeedforward based on FICD measurements, and TCI feedforward based onDICD measurements. As can be seen, overlap capacitance (C_(OV)) isadvantageously and significantly reduced by using one of the TCIfeedforward correction schemes. This reduction helps to increase deviceswitching speed. Also, power consumption figures in terms ofI_(off-Leak) and I_(on) are slightly better than what is achieved withconventional APC. As such it is seen from these simulation results thatTCI feedforward correction can be expected to provide devices withsignificantly reduced average power consumption (represented by I_(on)in Table 1), significantly reduced average parasitic capacitance, andrelatively small leakage current as compared to the No APC andConventional APC results of Table 1.

[0102] The above disclosure is to be taken as illustrative of theinvention, not as limiting its scope or spirit. Numerous modificationsand variations will become apparent to those skilled in the art afterstudying the above disclosure.

[0103] By way of example, the drive-current improvement steps of GardnerU.S. Pat. No. 5,863,824 may be employed concurrently with use of one ofthe TCI feedforward correction schemes disclosed herein. The CD controlsteps of Toprac U.S. Pat. No. 5,926,690 may be additionally oralternatively employed concurrently with use of one of the TCIfeedforward correction schemes disclosed herein.

[0104] Given the above disclosure of general concepts and specificembodiments, the scope of protection sought is to be defined by theclaims appended hereto.

[0105] [Note: Bracketed bold and italicized cross-referencing text isprovided in the below claims as an aid for readability and for findingcorresponding (but not limiting) support in the specification. Thebracketed text is not intended to add any limitation whatsoever to theclaims and should be deleted in all legal interpretations of the claimsand should also be deleted from the final published version of theclaims.]

What is claimed is:
 1. A Tilted Channel Implant (TCI) system [300] forperforming TCI operations [353′] on supplied production samples [150]having a gate structure [124] of directly or indirectly measured lengthand one or more sidewalls [144] of directly or indirectly measuredthickness, said TCI system comprising: (a) first error determining means[363] for determining an amount of error in each production samplebetween the measured sidewall thickness [swM] and a pre-defined, targetsidewall thickness [swT]; and (b) energy adjustment means [303] foradjusting TCI energy in response to the amount of error [SwM-Swt]determined by said first error determining means, where said adjustingof TCI energy at least partially counters deviation in depth of TCIdopants [355] due to said sidewall thickness error.
 2. The TiltedChannel Implant (TCI) system [300] of claim 1 and further comprising:(c) second error determining means [361] for determining an amount oferror in each production sample between the measured gate length [L2M]and a pre-defined, target gate length [L2T]; and (d) dosage adjustmentmeans [303] for adjusting TCI dosage in response to the amount of errordetermined by said second error determining means, where said adjustingof TCI dosage at least partially counters deviation in lateraldistribution of TCI dopants [355] due to said gate length error.
 3. TheTilted Channel Implant (TCI) system [300] of claim 2 wherein: (a.1) saidmeasured sidewall thickness [swM] is defined at least in part bymeasuring a pre-trim film thickness [F_(W)] of a material [132] that isdeposited to define said one or more sidewalls [144].
 4. The TiltedChannel Implant (TCI) system [300] of claim 2 wherein: (a.1) saidmeasured sidewall thickness [SwM] is defined at least in part bymeasuring a post-trim film thickness of a material [132] that isdeposited and thereafter trimmed to define said one or more sidewalls[144].
 5. The Tilted Channel Implant (TCI) system [300] of claim 2wherein said energy adjustment means [303] includes: (b.1) energyadjustment interpolating means [450] for interpolating approximateenergy adjustments based on two or more empirically established energyadjustments [E_(H),E_(L)].
 6. The Tilted Channel Implant (TCI) system[300] of claim 5 wherein said energy adjustment interpolating means[450] includes: (b.1a) linear or quasi-linear energy adjustmentinterpolating means [451,452] for interpolating approximate energyadjustments in accordance with a formula of the form: Energy_(a) =E₀*(1+βe _(SW) /S _(WT)) wherein E₀ is a prespecified amount of implantenergy used when sidewall thickness error e_(Sw) is zero, wherein saidmultiplying factor, β may either be a constant or a function of aspecified windowing range of the normalized error, e_(Sw)/S_(wT), andwhere S_(wT) is said target sidewall thickness.
 7. The Tilted ChannelImplant (TCI) system [300] of claim 6 wherein said multiplying factor, βis defined as one or more values selected from the range, 0.05≦β≦0.15where the selected value depends on the sign of e_(Sw)/S_(wT).
 8. TheTilted Channel Implant (TCI) system [300] of claim 5 wherein said dosageadjustment means [303] includes: (d.1) dosage adjustment interpolatingmeans [460,470] for interpolating approximate dosage adjustments basedon two or more empirically established implant dosage adjustments[D_(H),D_(L)].
 9. The Tilted Channel Implant (TCI) system [300] of claim8 wherein said dosage adjustment interpolating means includes: (b.1a)linear or quasi-linear energy adjustment interpolating means forinterpolating approximate energy adjustments in accordance with aformula of the form: Dose_(a)=Dose₀*(1+α((L _(2T) −L _(2M))//L_(2T))wherein Dose₀ is a prespecified amount of implant dosage used when gatelength error L_(2T)-L_(2M) is zero, wherein said second multiplyingfactor, a may either be a constant or a function of a specifiedwindowing range of the normalized error, (L_(2T)−L_(2M))/L_(2T), whereL_(2T) is said target gate length and where L_(2M) is said measured gatelength.
 10. The Tilted Channel Implant (TCI) system [300] of claim 9wherein said second multiplying factor, α is defined as one or morevalues selected from the range, 0.05≦α≦0.15 where the selected value orvalues for α may depend on the sign and/or windowed magnitude of(L_(2T)−L_(2M))/L_(2T).
 11. The Tilted Channel Implant (TCI) system[300] of claim 1 wherein said energy adjustment means [303] includes:(b.1) energy adjustment interpolating means [450] for interpolatingapproximate energy adjustments based on two or more empiricallyestablished energy adjustments [E_(H),E_(L)].
 12. The Tilted ChannelImplant (TCI) system [300] of claim 11 wherein said energy adjustmentinterpolating means [450] includes: (b.1a) linear or quasi-linear energyadjustment interpolating means [451,452] for interpolating approximateenergy adjustments in accordance with a formula of the form: Energy _(a)=E ₀*(1+β*e _(Sw) /S _(wT)) wherein E₀ is a prespecified amount ofimplant energy used when sidewall thickness error e_(Sw) is zero,wherein said multiplying factor, β may either be a constant or afunction of a specified windowing range of the normalized error,e_(Sw)/S_(wT), and where S_(wT) is said target sidewall thickness.
 13. Amachine-implemented method for performing Tilted Channel Implant (TCI)operations [353′] on supplied production samples [150] having a gatestructure [124] of directly or indirectly measured length and one ormore sidewalls [144] of directly or indirectly measured thickness, saidmethod comprising the steps of: (a) first determining [363] an amount offirst error in one or more production samples between the measuredsidewall thickness [swM] and a pre-defined, target sidewall thickness[swT]; and (b) adjusting TCI energy in response to the amount of firsterror [swM-SwT] determined by said first determining step, where saidadjusting of TCI energy at least partially counters deviation in depthof TCI dopants [355] due to said sidewall thickness error.
 14. Themachine-implemented TCI method of claim 13 and further comprising: (c)second determining [361] an amount of respective second error in saidone or more production samples between the measured gate length [L2M]and a pre-defined, target gate length [L2T]; and (d) adjusting TCIdosage in response to the amount of second error determined by saidsecond error determining step, where said adjusting of TCI dosage atleast partially counters deviation in lateral distribution of TCIdopants [355] due to said gate length error.
 15. The machine-implementedTCI method of claim 14 wherein: (a.1) said measured sidewall thickness[SwM] is defined at least in part by measuring a pre-trim film thickness[F_(w)] of a material [132] that is deposited to define said one or moresidewalls [144].
 16. The machine-implemented TCI method of claim 14wherein: (a.1) said measured sidewall thickness [swM] is defined atleast in part by measuring a post-trim film thickness of a material[132] that is deposited and thereafter trimmed to define said one ormore sidewalls [144].
 17. The machine-implemented TCI method of claim 14wherein said energy adjusting step includes: (b.1) interpolating [450]approximate energy adjustments based on two or more empiricallyestablished energy adjustments [E_(H),E_(L)].
 18. Themachine-implemented TCI method of claim 17 wherein said energyadjustment interpolating step [450] includes: (b.1a) using linear orquasi-linear energy adjustment interpolation [451,452] for interpolatingapproximate energy adjustments in accordance with a formula of the form:Energy_(a) =E ₀*(1+βe _(Sw) /S _(wT)) wherein E₀ is a prespecifiedamount of implant energy used when sidewall thickness error e_(Sw) iszero, wherein said multiplying factor, β may either be a constant or afunction of a specified windowing range of the normalized error,e_(Sw)/S_(wT), and where S_(wT) is said target sidewall thickness. 19.The machine-implemented TCI method of claim 18 wherein said multiplyingfactor, β is defined as one or more values selected from the range,0.05≦β≦0.15 where the selected value depends on the sign ofe_(Sw)/S_(wT).
 20. The machine-implemented TCI method of claim 14wherein said dosage adjusting step [303] includes: (d.1) using dosageadjustment interpolation [460,470] for interpolating approximate dosageadjustments based on two or more empirically established implant dosageadjustments [D_(H),D_(L)].
 21. The machine-implemented TCI method ofclaim 20 wherein said dosage adjustment interpolating step includes:(b.1a) using linear or quasi-linear energy adjustment interpolation forinterpolating approximate energy adjustments in accordance with aformula of the form: Dose _(a) =Dose ₀* (1+α(L _(2T) −L _(2M))/L _(2T))wherein Dose₀ is a prespecified amount of implant dosage used when gatelength error L_(2T)−L_(2M) is zero, wherein said second multiplyingfactor, α may either be a constant or a function of a specifiedwindowing range of the normalized error, (L_(2T)−L_(2M))/L_(2T), whereL_(2T) is said target gate length and where L_(2M) is said measured gatelength.
 22. The machine-implemented TCI method of claim 21 wherein saidsecond multiplying factor, α is defined as one or more values selectedfrom the range, 0.05≦α≦0.15 where the selected value or values for α maydepend on the sign and/or windowed magnitude of (L_(2T)−L_(2M))/L_(2T).(claims 1-22 of parent case are canceled in this divisional)
 23. Acomputer system [301-303] for use in a mass production stream whereinupstream production samples [150] each have at least one of a gatestructure [124] of directly or indirectly measured length and one ormore adjacent gate sidewalls [144] of directly or indirectly measuredthickness, and wherein production results [Leff] of downstreamproduction steps [352] are affected by said at least one of the gatestructure length [L2′] and the one or more gate sidewall thicknesses[Sw], said computer system comprising: (a) error determining means [360]for determining one or more corresponding amounts of error in one ormore production samples between the measured sidewall thickness [SwM]and a pre-specified, target sidewall thickness [SwT] or between themeasured gate length [L2M] and a pre-defined, target gate length [L2T];(b) error signal forwarding means [362,364] for feeding forward errorsignals representing said corresponding amounts of error; and (c)downstream compensating means [303,352] for receiving said fed forwarderror signals and for post-compensating for errors, if any, indicated bythe fed forward error signals.
 24. The computer system [301-303] ofclaim 23 wherein said downstream compensating means includes: (c.1) aTilted Channel Implant (TCI) subsystem [352] having at least one ofvariable implant energy parameter and a variable implant dosageparameter, where at least one of said implant parameters is responsiveto at least one of said fed forward error signals.
 25. The computersystem [301-303] of claim 24 wherein said error determining means [360]includes: (a.1) first error determining means [363] for determining afirst amount of error in one or more production samples betweenrespective measured sidewall thicknesses [SwM] and the pre-specified,target sidewall thickness [swT].
 26. The computer system [301-303] ofclaim 25 wherein said error determining means [360] includes: (a.2)second error determining means [361] for determining a second amount oferror in one or more production samples between respective measured gatelengths [L2M] and the pre-defined, target gate length [L2T].
 27. Thecomputer system [301-303] of claim 24 wherein said downstreamcompensating means includes: (c.2) energy parameter adjustmentcalculating means for defining adjustments to said variable implantenergy parameter using an interpolation [450] based on one or moreempirically established energy adjustments [E_(H),E_(L)].
 28. Thecomputer system [301-303] of claim 27 wherein (c.2a) said energyadjustment interpolation [450] uses linear or quasi-linear energyadjustment interpolation [451,452] for interpolating approximate energyadjustments in accordance with a formula of the form: Energy_(a) =E₀*(1+β*e _(Sw) /S _(wT)) wherein E₀ is a prespecified amount of implantenergy used when sidewall thickness error e_(Sw) is zero, wherein saidmultiplying factor, β may either be a constant or a function of aspecified windowing range of the normalized error, e_(Sw)/S_(wT), andwhere S_(wT) is said target sidewall thickness.
 29. The computer system[301-303] of claim 28 wherein said multiplying factor, β is defined asone or more values selected from the range, 0.05≦β≦0.15.
 30. Thecomputer system [301-303] of claim 24 wherein said downstreamcompensating means includes: (c.2) dosage parameter adjustmentcalculating means for defining adjustments to said variable implantdosage parameter using an interpolation [460] based on one or moreempirically established dosage adjustments [D_(H),D_(L)].
 31. Thecomputer system [301-303] of claim 30 wherein (c.2a) said dosageadjustment interpolation [460] uses linear or quasi-linear dosageadjustment interpolation for interpolating approximate dosageadjustments in accordance with a formula of the form: Dose _(a) =Dose₀*(1+α((L _(2T) −L _(2M))/L _(2T)) wherein Dose₀ is a prespecifiedamount of implant dosage used when gate length error L_(2T)−L_(2M) iszero, wherein said second multiplying factor, a may either be a constantor a function of a specified windowing range of the normalized error,(L_(2T)−L_(2M))/L_(2T), where L_(2T) is said target gate length andwhere L_(2M) is derived from one or more measured gate lengths.
 32. Themachine-implemented TCI method of claim 31 wherein said secondmultiplying factor, α is defined as one or more values selected from therange, 0.05≦α≦0.15.
 33. An instructions conveying article for conveyinginstructions to a compatible and configurable computer system [301-303],where said computer system is for use in a mass production streamwherein upstream production samples [150] each have at least one of agate structure [124] of directly or indirectly measured length and oneor more adjacent gate sidewalls [144] of directly or indirectly measuredthickness, and wherein production results [Leff] of downstreamproduction steps [352] are affected by said at least one of the gatestructure length [L2′] and the one or more gate sidewall thicknesses[Sw], said conveying instructions causing the computer system to performthe steps of: (a) determining [360] one or more corresponding amounts oferror in one or more production samples between the measured sidewallthickness [SwM] and a pre-specified, target sidewall thickness [se] orbetween the measured gate length [L2M] and a pre-defined, target gatelength [L2T]; and (b) feeding forward [362,364] error signalsrepresenting said corresponding amounts of error to a downstreamcompensating means [303,352], where said downstream compensating meanspost-compensates for errors, if any, indicated by the fed forward errorsignals.
 34. An improved, second mass production process [500] forproducing integrated circuit devices [150] each having, in a firstproduct-precursor form [140], at least one of a gate structure [124] ofdirectly or indirectly measured length and one or more adjacent gatesidewalls [144] of directly or indirectly measured thickness, andwherein production results [Leff] of downstream production steps [352],where the production results are derived from the firstproduct-precursor form [140], are affected by said at least one of thegate structure length [L2′] and the one or more gate sidewallthicknesses [sw] of the first product-precursor form, wherein theimprovement is over a first mass production process and the first massproduction process is characterized by at least below aspects (1.1) and(1.5) as well as by at least one or the other of aspects (1.3) and(1.4): (1.1) a first predefined one [510] of first process toleranceranges, the first predefined range being applicable to a secondproduct-precursor form [100] and being denoteable as e₁<e_(GatePR)≦e₂,where e_(GatePR)=L_(PRT)-CD_(PRT), represents a difference between anideal length, L_(PRT) and a correspondingly measured length, CD_(PRT),for a developed photoresist feature [118,119], of the secondproduct-precursor form [100], either before or after a PR trimmingprocess [512] is carried out on said developed photoresist feature, andthe first mass production process is further characterized by a deemingas out of tolerance [516], those measured specimens of the secondproduct-precursor form whose measured length, CD_(PRT), causese_(GatePR) to be outside said first predefined range; (1.2) a secondpredefined one [520] of first process tolerance ranges, the secondpredefined range being applicable to a third product-precursor form[120] and being denoteable as e₃≦e_(GateEtched)≦e₄ wheree_(GateEtched)=L_(2′T)−L_(2′M), represents a difference between an ideallength, L_(2′T) and a correspondingly measured length, L_(2′M), for anetched gate feature [124] of the third product-precursor form [120], andthe first mass production process is further characterized by a deemingas out of tolerance [526], those measured specimens of the thirdproduct-precursor form whose measured length, L_(2′M) causese_(GateEtched) to be outside said second predefined range; (1.3) a thirdpredefined one [530] of first process tolerance ranges, the thirdpredefined range being applicable to a fourth product-precursor form[130] and being denoteable as e₅≦e_(Depo)≦e₆ wheree_(Depo)=F_(wT)−F_(wM) represents a difference between an idealdeposition thickness, F_(wT) and a correspondingly measured depositionthickness, F_(wM), for a sidewall precursor film [132], of the fourthproduct-precursor form [130], and the first mass production process isfurther characterized by a deeming as out of tolerance [536], thosemeasured specimens of the fourth product-precursor form whose measureddeposition thickness, F_(wM) causes e_(Depo) to be outside said thirdpredefined range; (1.4) a fourth predefined one [540] of first processtolerance ranges, the fourth predefined range being applicable to afifth product-precursor form [140] and being denoteable ase₇≦e_(SW—trim)≦e₈ where e_(SW—trim)=S_(wM)−S_(wT) represents adifference between an ideal post sidewall-trim thickness, S_(wT) and acorrespondingly measured post sidewall-trim thickness, S_(wM), for oneor more trimmed sidewalls [144] of the fifth product-precursor form[140], and the first mass production process is further characterized bya deeming as out of tolerance [546], those measured specimens of thefifth product-precursor form whose measured post sidewall-trimthickness, S_(wM) causes e_(SW—trim) to be outside said fourthpredefined range; (1.5) a Tilted Channel Implant (TCI) [552] performedon the first product-precursor form after at least one of said etchedgate feature [124] and said one or more trimmed sidewalls [144] areformed; said improved, second mass production process [500] beingcharacterized by: (a) adjusting [550] at least one of TCI energy and TCIdosage in response to deviation from a corresponding ideal dimension asdetected by a corresponding one or more of said production measurementsteps in corresponding ones of characterization aspects (1.1)-(1.5); and(b) a set of second process tolerance ranges, wherein at least one ofthe tolerance ranges in the second set is wider than a correspondingtolerance range in the first set.
 35. The improved, second massproduction process [500] of claim 34 wherein said adjusting of the TCIincludes automatic adjusting of TCI energy in response to deviation insidewall thickness using an interpolation [450] based on one or moreempirically established energy adjustments [E_(H),E_(L)].
 36. Theimproved, second mass production process [500] of claim 35 wherein saidenergy adjustment interpolation [450] uses linear or quasi-linear energyadjustment interpolation [451,452] for interpolating approximate energyadjustments in accordance with a formula of the form: Energy _(a) =E₀*(1+β*e _(Sw) /S _(wT)) wherein E₀ is a prespecified amount of implantenergy used when sidewall thickness error e_(Sw) is zero, wherein saidmultiplying factor, β may either be a constant or a function of aspecified windowing range of the normalized error, e_(Sw)/S_(wT). 37.The improved, second mass production process [500] of claim 34 whereinsaid adjusting of the TCI includes automatic adjusting of TCI dosage inresponse to deviation in gate length using an interpolation [460] basedon one or more empirically established energy adjustments [D_(H),D_(L)].38. The improved, second mass production process [500] of claim 37wherein said dosage adjustment interpolation [460] uses linear orquasi-linear dosage adjustment interpolation for interpolatingapproximate dosage adjustments in accordance with a formula of the form:Dose _(a) =Dose ₀*(1+α(L _(2T) −L _(2M))/L _(2T)) wherein Dose₀ is aprespecified amount of implant dosage used when gate length errorL_(2T)−L_(2M) is zero, wherein said second multiplying factor, a mayeither be a constant or a function of a specified windowing range of thenormalized error, (L_(2T)−L_(2M))/L_(2T), where L_(2T) is said targetgate length and where L_(2M) is derived from one or more measured gatelengths.
 39. The improved, second mass production process [500] of claim34 wherein said first mass production process is characterized by aspect(1.2).
 40. The improved, second mass production process [500] of claim39 wherein under-etched specimens of the third product-precursor formare further etched [528] and remeasured for error.
 41. The improved,second mass production process [500] of claim 34 wherein over-depositedspecimens of the of the fourth product-precursor form are exposed to acompensating, isotropic pre-etch [538] before said sidewalls are formedby anisotropic trimming [542].